In many integrated circuit applications, for example in many non-volatile memory products such as an Erasable Programmable Read Only Memory (EPROM), a Flash Memory, an Electronically Erasable Programmable Read Only Memory (EEPROM), etc., there is the need to have different positive and negative voltages higher than the external Power Supply Voltage (VCC) to permit all kinds of operation that the integrated circuit application, for example a memory system, requires. Examples of such an operation is the reading of data stored in the memory system, programming of data into the memory system and erase data that are stored in the memory system.
Each one of these operations requires different voltage levels in order to bias different electronic circuits, positive voltages as well as negative voltages.
There are many realizations of a voltage generator circuit that provides a higher voltage than the external power supply voltage. Most of them use several stages based on capacitive elements.
The optimization of high voltage generators is related to area occupation, efficiency (with regard to power consumption/output power), voltage gain (Vout/VCC) reliability and current capability.
With regard to the area occupation, the capacitance area has to be taken into account, that is the area used for capacitances in the integrated circuits. As a generic example an ideal two-plate capacitance is considered, which has a capacitance value according to
                    C        =                  ɛ          ⁢                                    A              d                        .                                              (        1        )            
In common semiconductor technology, the capacitance has the parallel plates been developed vertically (d), while the area (A) is designed horizontally d and ε are fixed, that is predetermined by the technology process used for manufacturing the integrated circuit. Therefore, in order to increase the capacitance value of the capacitance, the area A should be increased what obviously has a severe impact on the die area needed for the capacitance area.
Furthermore, areas are required in the integrated circuit for different circuitries, for example for high voltage switches, a phase generator circuit or a pre-charge circuit.
With regard to the efficiency as optimization criterion, wherein the efficiency is defined by the power that is needed to supply all the stages of the integrated circuit from VCC, that is the external power supply voltage and the power that is provided to the load of the voltage generator circuits, that is the output power. The power spent to charge parasitic capacitances like for charging junction capacitances can be relevant for the efficiency.
The voltage gain is defined as the output voltage from the voltage generator circuit divided by the external power supply voltage (VCC). For some applications, the voltage gain is more important than the above and the following mentioned optimization criteria (pure capacitive load).
With regard to the reliability, care should be taken in the implementation to avoid forward biased junctions that can trigger latch up, current injection due to high voltage change, oxide and junction stress due to overvoltage.
Current capability is to be understood as the maximum current capability at the regulated voltage that for the typical implementation is determined according to the following formula:I=C·ΔV·f.  (2)
The comparison will be carried out for a normalized frequency and capacitance according to the following equation:
                              I          capability                =                                            I              out                                                      C                tot                            ·              f                                .                                    (        3        )            
FIG. 14A shows an example of a common charge pump circuit 1400 as a known voltage generator circuit. The charge pump circuit 1400 includes a series of diodes D1, D2, D3, DOUT and capacitances CT1, CT2, CTN, CSTORE. The diodes D1, D2, D3, DOUT are required to establish the direction of the current flow, while the main task of the capacitances CT1, CT2, CTN, CSTORE is to accumulate the charge that is then transferred from one capacitance to the next capacitance, by driving the capacitances with the phase signals CK and CK# (see FIG. 14B).
Two physical phenomena are the basis for the operation of the charge pump circuit 1400. The first physical phenomena is related to the basic capacitance characteristic: the voltage across the capacitance cannot change instantaneously. The second physical phenomenon is the so-called charge sharing phenomenon, which takes place when two capacitances pre-charged at different voltages are connected. The final voltage of this connected node between the two capacitances depends on the initial voltages of the two capacitances as well as on their relative dimensions.
The operation mode of the charge pump circuit 1400 includes a pre-charge phase and an operation phase. Within the pre-charged phase, all nodes Si that is S1, S2, SN are initially pre-charged to the external power supply voltage VDD. After the pre-charge phase, the charge pump phase starts with the power up of the CK signal and the CK# signal, thereby beginning to charge the start and to transfer the charge.
When the CK signal goes from the ground potential to the external power supply voltage VDD (time instant t1 in FIG. 14B), the first node S1 becomes equal to approximately 2* VDD. At this point, a portion of the charge previously stored in the first capacitance CT1 is transferred to the second capacitor CT2. The transfer of the charge stops ideally when the voltage of the second node S2 is equal to the voltage of the first node S1. The first diode D1 prevents the charge from going back to the supply of the circuit, for ensuring the charge to go into the second capacitor CT2. Thus, the voltage at the second capacitor CT2 rises.
When the CK signal goes from the power supply voltage VDD to ground potential (time instant t2 in FIG. 14B), the CK# signal rises from the ground potential to the power supply voltage VDD and the second capacitance CT2 then transfers a portion of its stored charge to the third capacitance CTN, thereby increasing the voltage at the third capacitance CTN. At the same time, the first capacitance CT1 that partially discharged during the previous phase is recharged to the value of the power supply voltage VDD.
It should be noted that the voltage that is transferred from one capacitance to the next capacitance in addition to the voltage of the previous capacitance decreases from node to node with the same value of the capacitances.
Therefore, the voltage of the output node continues to increase by an increment that becomes smaller and smaller until the output voltage Vout reaches the value of (VDD+n*VDD), wherein n is equal to the number of stages of the charge pump circuit 1400, while the internal node voltages reach a maximum value of (V(Sn)=VDD+n*VDD). As soon as these voltages are reached, no further charge transfer across the diodes takes place.
In this context, it should be mentioned that at the charge pump phase, all capacitances are always provided with a respective external voltage, either the voltage coming from the external input terminal and thus the external pulse apply voltage VDD or with the CK signal or the CK# signal. The CK signal and the CK# signal are alternating signals that are inverse to each other.
The charge pump circuit 1400 can theoretically increase the input voltage by the factor n*VDD, but it takes a long time and a lot of clock cycles in order to increase the input voltage. Furthermore, usually a rather complex logic for controlling the charge pump circuit 1400 is required and in addition, a clock circuit is required to provide the CK signal and its inverse signal, namely the CK# signal.
FIG. 15A illustrates another voltage generator circuit, which is also called a voltage boosting circuit 1500. The boosting circuit 1500 includes a boost capacitance CBOOST and a load capacitance CLOAD, wherein a first node of the boost capacitance CBOOST and a first node of the load capacitance CLOAD are connected with each other at a node BN. A first source/drain region of a PMOS field effect transistor 1501 is also coupled to the node BN, the second source/drain region of the PMOS field effect transistor 1501 is coupled to the power supply voltage VDD. The gate region of the PMOS field effect transistor 1501 receives the signal A (see FIG. 15B).
The second node of the boost capacitance CBOOST is coupled to the output inverter 1502, which receives the signal B at its input (see FIG. 15C).
In the following, the working principal of the boosting circuit 1500 will be described in detail.
At the beginning, the boost capacitance CBOOST and the load capacitance CLOAD are pre-charged to the power supply voltage VDD via the PMOS field effect transistor 1501.
When the boost of the node BN is required, the PMOS field effect transistor 1501 is turned off and then the second signal B is driven low. In this way, the lower plate of the boost capacitance CBOOST is biased at a voltage equal to the power supply voltage VDD. Since the node BN is isolated, its potential can be calculated by charge conservation. The charge Qi that is present on the pre-charge can be written asQi=(CBOOST+CLOAD)·VDD.  (4)
The final charge that is the charge when the boost has occurred is equal toQf=CBOOST·(VBN−VDD)+CLOAD·VBN.  (5)
By imposing Qi=Qf, it follows that the value of the potential on node BN after the boost operation is equal to
                              V          BN                =                              V            DD                    +                                                    C                BOOST                                                              C                  BOOST                                +                                  C                  LOAD                                                      ·                                          V                DD                            .                                                          (        6        )            
FIG. 15D shows the time schedule of the potential at node BN.
The boosting circuit 1500 is limited in its capability of the maximum achievable voltage gain, that is the boosting circuit 1500 can increase the output voltage up to twice the input voltage if the input voltage is the external power supply voltage VDD and the boost voltage VBOOST.
What is therefore needed is an improved voltage generator circuit architecture and a corresponding method for providing an output voltage.